High level synthesis using Vivado HLS for Zynq SoC: Image processing case studies

Abstract

In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool are presented and compared with hand-coded designs. In Vivado HLS, the designer has the opportunity to employ libraries similar to OpenCV, a library that is well-known and wide used by software designers. The algorithms are compared in terms of area resources in two conditions: using the libraries and not using the libraries. The case studies are Data Binning, a Step Row Filter and a Sobel Filter. These algorithms have been selected because they are very common in the field of image processing and they have high computational complexity. The main benefit of the Vivado HLS tool is the reduction in time-to-market. On the other hand, when a software designer hand-codes the design, the use of image processing libraries similar to OpenCV helps to reduce development time even further because software designers are familiar with them. However, using these kinds of libraries significantly increases the necessary FPGA resources.