Latency estimation and optimization for DSP blocks in high level synthesis stage

Abstract

The DSP blocks on modern FPGAs are highly capable and support a variety of different multiplication operation. High level synthesis is one of the important DSP block development tools. the tool needs accurate estimation latency of the DSP block application circuit in order to produce good design solutions while converts the C++ code to Verilog code. Especially DSP blocks have pipeline structure, the latency estimation is more important. We propose a machine learning method which can accurate estimation minimum latency of DSP block multiplication application circuit in high level synthesis. The experiments show that the proposed approach is more accurate than Vivado-Hls to estimate the latency of DSP block application circuit. Sometimes the same clock frequency, using the method of this paper, the DSP application circuit can save 50% latency than the Vivado HLS tool.