A Detailed Illustration of VLSI Block Design Implementation Process Using VIVADO HLS and Arty Kit

Abstract

This paper aims to provide consolidated procedure to design and implement VLSI block in Arty A7 kit using VIVADO HLS. Sine wave signal with appropriate pulse width is implemented and default hardware part is selected in VIVADO HLS tool and verilog code has been written in VIVADO IDE for the implementation of Arty A7 kit. Using high level synthesis, an engineer has the contingency to add libraries for the corresponding project and further proceeds with the achievement at superior level of entrancement. The procedure of implementing sinusoidal signal and the performance of implementation in Arty A7 kit using vivado HLS is illustrated along with simulation, synthesis, implementation results and project summary report. Timings, Design rule check (DRC) violations, utilization, total on-chip power are charted in project summary report. The proposed research work is based on FPGA implementation based image compression/decompression using VIVADO HLS. Proposed work is widely used in medical application especially in telehealth where patient records are transferred from remote area to the hospital to make consultation in easier manner. Likewise FPGA implementation based image compression/ decompression is used in fields like remote sensing, oceanography, earth observation etc. to predict the future weather conditions and it helps to take precautionary steps in order to detect the disaster before it occurs. Initial proposed research work has been done based on FPGA implementation of sinusoidal signal using VIVADO HLS. Future research work, FPGA implementation based image compression/decompression will be carried out using VIVADO HLS. The main advantage of Vivado HLS tool is to obtain high speed performance and low power consumption while implementing in hardware.