Abstract
A new hierarchical layout vs. schematic (LVS) comparison system for layout verification has been developed. The schematic hierarchy is restructured to remove ambiguities for consistent hierarchical matching. Then the circuit hierarchy is reconstructed from the layout netlist by using a modified SubGemini algorithm recursively in bottom-up fashion. For efficiency, simple gates are found by using a fast rule-based pattern matching algorithm during preprocessing. Experimental results show that our hierarchical netlist comparison technique is effective and efficient in CPU time and in memory usage, especially when the circuit is large and hierarchically structured.
Highlights
Most designs are specified at the behavioral level
We propose a new hierarchical netlist comparison technique, which compares a hierarchical netlist and a flattened netlist, for layout verification based on refining and hierarchy restructuring
We implemented our hierarchical layout vs. schematic (LVS) (HLVS) comparison algorithm on a Sun Ultra SPARC workstation running at 296 MHz by using the C programming language
Summary
Most designs are specified at the behavioral level. They are transformed to the register transfer level (RTL), to the gate level, and to the layout description. One major task of chip-level verification is consistency proof between the original schematic netlist and the one extracted from the layout. This verification problem can be modeled as a graph isomorphism problem. If the number of nodes in these partitions is small (possibly only one), the number of comparison operations decreases drastically and isomorphism can be tested in acceptable computing time for a large number of nodes [1]
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