Hardware Trojan Detection at Behavioral Level Using Inline Assertions and Verification Using UVM

Abstract

Recently, hardware Trojan (HT) is posing a significant challenge to the integrated circuit (IC) industry and has inspired various improvements in the Trojan identification plans. This research study presents the inline assertions for the detection of hardware Trojan at the behavioral level of a system on chip (SoC). In the proposed RTL design, a modified circuit design flow is suggested to incorporate inline assertions into a SoC. Flexible inline assertions are developed in the RTL block within the design module. The router IP design and inline assertions are synthesized and implemented in Xilinx Vivado and Aldec Rivera Pro using Verilog HDL. The universal verification methodology (UVM) is also used to verify the proposed design with the different test case scenarios. The functional coverage and code coverage are analyzed in Aldec Rivera Pro. Parameters such as power and area are analyzed in the Synopsys design compiler (DC).