Abstract

The increasing concern about the security and reliability of abroad manufactured integrated circuits (ICs) has attracted academia and industries to develop hardware Trojan (HT) detection approaches. This article presents an efficient integrated HT detection technique based on evaluating changes in the integrated parasitic capacitors. The HT detection circuit consists of a capacitively coupled, low-power, low-noise, operational transconductance amplifier (OTA), which can detect capacitance fluctuations in the range of 10 aF. The HT detection circuit consumes <inline-formula> <tex-math notation="LaTeX">$5.88~\mu \text {W}$ </tex-math></inline-formula> from 1.8-V power supply in 180-nm CMOS technology. The detection method is based on clustering the IC and monitoring each cluster&#x2019;s flag. The flag set circuit is designed to sense parasitic capacitance and change its status based on it. The proposed technique can detect the HT circuit before the activation of the IC. Moreover, this technique shows very promising results in detecting HTs with zero-delay effect, which is a challenging issue in the conventional delay-based side-channel signal analysis method. More significantly, the proposed method does not require a golden IC for HT detection and can detect the HT using simulation-based data. The proposed method creates a recognizable difference detection signal between the capacitive behavior of an infected and a pure IC. This results in a high confidence level in the proposed detection method. The proposed idea is implemented on ISCAS&#x2019;85 benchmark circuits, and the detection outcomes and the statistical simulations are presented.

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