Hardware - software co-design framework for sum of absolute difference based block matching in motion estimation

Abstract

Motion estimation is the computationally intensive part of video encoding. This paper presents a processing element based architecture for accelerating the calculation of Sum of Absolute Differences (SAD) which is the most widely used block matching criteria in motion estimation. A clock gating method is anlysed to enable or disable the required processing elements for a particular time of use. The selection of processing elements is performed based on motion analysis of the input video. The level of motion is estimated from initial frames to configure the hardware for SAD evaluation. A System-on-Chip approach, implemented in Xilinx Zynq SoC is proposed that will be efficient in terms of power and resource utilization as the hardware is configured based on the property of input video. This hardware-software co-design is able to achieve approximately 4.6x speed up compared to the the original software implementation of the framework running on ARM processor.