Abstract
(bcdP*H.264/AVC ef dP6ghi)2RjkXWl*m(motion estimation, ME) &n o. IP(intellectual property) KpETHq. m *rs(buffer), PU tk(processing unit array), SAD uv(SAD selector), MV wx(motion vector generator) yDExlzq. PU tk*16=PUExlz, {{PU*16=PE(processing element)Ek|}zq. . &n~ei/ 8Y k T]tko]? q*SAD)2FGk2Fzq*kq. T m *Altera ?FPGAeStatixEP3SE80F1152C2dP3%$9?H, ` &nF*446.43MHzkq. PT *1080p _` 50fpsEV8Fzq. AbstractIn this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixEP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.Keyword : Data reuse, H.264/AVC standard, Motion Estimation, memory access reduction, Inter predictionBbc
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