Comparative analysis of parallel SAD calculation hardware architectures for H.264/AVC video coding

Abstract

Sum of Absolute Difference (SAD) is a low complexity distortion metric widely employed in the mode decision stage of real-time video encoders. In H.264/AVC encoding, the state-of-the-art video coding standard, motion estimation responds for the most computational complexity, most of it coming from the SAD calculation for all the candidate blocks. Considering an H.264/AVC motion estimation hardware architecture [5], SAD calculation stands for 79% of total gate count. Therefore, focusing on SAD hardware design space exploration can result in important area, power and performance improvement of H.264/AVC ASIC video encoders, but such exploration were not investigated in previous works. Concerning this question, this work firstly presents a comparative analysis of nine hardware architecture alternatives for SAD calculation processing unit, varying the parallelism level (4, 8 and 16 samples in parallel) and the number of pipeline stages. The comparison is presented in terms of total gate count, processing cycles, throughput, power and energy consumption. Results shown that fewer stage pipeline versions achieved fewer energy consumption and higher throughput (operating at a restricted clock frequency) when compared with deeper pipeline versions. These analyses are useful to select the best SAD architectural alternative to fit each application requirement, from low-power mobile to high resolution H.264/AVC on-chip video encoder.