Hardware security and split fabrication

Abstract

As hardware system designers include third party IPs in their designs and outsource the fabrication to off-shore facilities, hardware security threats are becoming more serious. Threats include the overbuilding and malicious circuit insertion at the foundry during fabrication. Split fabrication for both 2D, 2.5D, and 3D ICs has been suggested to overcome these threats. In split fabrication, the system designer partitions the system into two parts: a complex part and a simple part. The complex part includes all the advanced circuitry that needs to be fabricated in a high-end untrusted fabrication facility. However, without the simple part, it is difficult for the untrusted foundry to identify the functionality of the system. The simple part is fabricated and integrated with the complex part in a trusted old foundry. This paper explores the use of an optimized set of isomorphic cells to implement digital systems. The use of these optimized cells should make it harder for the untrusted foundry to understand the system while simplifying the fabrication and integration process at the trusted foundry. The trade-off between simplifying the fabrication process at the trusted facility and the area overhead is studied on combinational benchmarks. The experimental results indicate that an average of 20% effort reduction can be achieved while maintaining a negligible impact on the area and delay of the original design.