Taxonomy of hardware security methodologies: IP core protection and obfuscation

Abstract

In the modern electronic era, the increased usability and acceptability of reusable intellectual property (IP) cores induce the necessity to secure them from various hardware security threats and attacks. This chapter presents a taxonomy of hardware security methodologies for IP cores and a detailed design flow of hardware integrated circuits (ICs) along with vulnerability points where potential attacks/threats are possible. Trustworthy and untrustworthy regimes in the design flow have also been highlighted in the discussion. Further, a discussion of detective and preventive control-based hardware security approaches used for hardware IP cores have also been presented, including an analysis of prominent structural obfuscation, logic locking (logic encryption), and IP core protection (IPP) techniques. Each approach has been lucidly explained in terms of its threat model, algorithm, and security analysis. Finally, a security comparison of hardware IP obfuscation approaches in terms of strength of obfuscation security metric as well as security comparison of IPP approaches in terms of probability of coincidence security metric have also been introduced.