Towards Performance Optimization of Ring Oscillator PUF using Xilinx FPGA

Abstract

A Field Programmable Gate Array (FPGA) is a general-purpose semiconductor device made up of interconnected configurable logic blocks, which the end-user can configure to implement and operate the required logic, from a simple logic gate to a sophisticated system on a chip. Nevertheless, FPGAs can be vulnerable to security threats such as reverse engineering, cloning, and overbuilding attacks. Physically unclonable functions (PUFs) have been introduced as leading, robust, low-cost solutions against different hardware security threats. PUFs are hardware security primitives which operate as a one-way function that produces a unique output from the same input and the same PUF circuit implemented on different boards. As a result, PUFs output can be used as a “digital fingerprint” to identify electronic devices/systems uniquely, and it can be used in different security scenarios. This study presents the optimization of one of the most PUF types implemented in hardware security applications, called ring oscillator PUF or ROPUF. The presented ring oscillator PUF shows outstanding performance in terms of uniqueness and bit-aliasing with less hardware compared to the related work.