Hardware Optimized Approximate Adder with Normal Error Distribution

Abstract

This paper presents a new hardware optimized approximate adder that has practically zero average error and a normal i.e., a Gaussian error distribution. We call the proposed approximate adder HOAANED, which is expanded as hardware optimized approximate adder with a normal error distribution. We considered the use of HOAANED for digital image processing alongside the accurate adder and many other approximate adders for a practical analysis. In particular, the additions involved in performing fast Fourier Transform and inverse fast Fourier transform operations to reconstruct the images were implemented using accurate and approximate adders separately. We found that HOAANED improves the peak signal-to-noise ratio of the reconstructed images better compared to the other approximate adders. Further, HOAANED has optimized design metrics. This observation is based on physical implementation using a 32/28nm CMOS standard digital cell library. Furthermore, based on the error analysis of many 32-bit approximate adders using a million random input vectors we found that HOAANED has practically zero average error, an optimized root mean square error and a normal error distribution.