Hardware Implementation of Multilevel Two Dimensional Haar Wavelet Transform Using FPGA

Abstract

Focusing on the intensive computations involved in the discrete wavelet transform (DWT), the design of efficient hardware architectures for a fast computation of the transform has become imperative, especially for real-time applications. To constrain the complexities of the design, a basic linear algebra approach is used to denote the signal flow graph of forward DWT (FDWT) and inverse DWT (IDWT) architectures. Based on this context, the DWT was selected along with the theorized Haar function being the mother wavelet, as the main analytical method for this study. The proposed FDWT and its IDWT hardware architecture filter generated similar results compared to the MATLAB model for the seven levels of DWT decomposition. Simulations were performed using grayscale images of different sizes to validate the proposed design and attain speed performance appropriate for a number of realtime applications. The proposed FDWT filter produced 700 slices of hardware logic and register element area, which comprises less than 2 % of the Altera DE2 development board Cyclone II Field Programmable Gate Array (FPGA) hardware area.