Abstract
In this study, successful real-time implementation of discrete-time chaotic zigzag map as a Random Number Generator on field-programmable gate array (FPGA) environment is presented. For hardware implementation, in addition to ready-use circuit elements defined on 32-bit floating-point numbers, very high-speed integrated circuit hardware description language (VHDL) is used. In the scope of this study, cryptographic critical competencies such as system reliability and randomness quality related to nonlinear dynamic behaviour of zigzag map are examined. H function post - processing technique is used in the system for random numbers with low statistical quality achieved from chaotic system. Also NIST 800-22 standard test technique is used for statistical verification of bit sequences obtained from the generator. In addition to its practical applicability, the results show that the zigzag map can be used as a random number generator for embeded cryptographic applications.
Highlights
In addition to cryptography, randomness is a common statistical concept for many areas such as game theory, simulation, statistic, quantum mechanics, programming and entertainment
The 8-bit random numbers generated by Pseudo Random Number Generators (PRNG) every 208 clock pulses, and the 32-bit outputs of the zigzag map are recorded in two different memory architectures for testing purposes, as in Fig. 7 (A) and (B)
The bit-level random outputs of PRNG are obtained from the trajectory produced by the chaotic zigzag map for the initial value of x
Summary
Randomness is a common statistical concept for many areas such as game theory, simulation, statistic, quantum mechanics, programming and entertainment. In discrete time, where the evolution of the system depends on the values of state variables, chaotic systems are expressed by simple non-linear equations [3, 8] For both chaotic system models, exponential sensitivity to the initial conditions and the ability to produce long-term non-periodic oscillations are the basic characteristics of these systems coinciding with the pattern of random behavior. There are different chaos-based PRNG and TRNG paradigms implemented with FPGA chips offering important facilities such as flexibility, ease of modelling, low power consumption, parallel processing and speed Some of these studies can be summarized as follows: Özkaynak [7] proposed an applicable RNG model on FPGA chips, which could be an alternative to discrete time chaotic systems using the fractional order Chua system.
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