Gate Insulator Engineering in Top-Gated Indium-Tin-Oxide-Stabilized ZnO Thin-Film Transistors

Abstract

This letter proposes a high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO2 stack for thin-film transistors (TFTs), which contains a layer of SiH4-sourced PECVD SiO2 (SiH4-SiO2) with a layer of tetraethyl-orthosilicate (TEOS)-sourced PECVD SiO2 (TEOS-SiO2) underneath. The issues of high hydrogen content in the SiH4-SiO2 and rich hydroxyl groups in the TEOS-SiO2 were found to be well addressed by capping the TEOS-SiO2 with SiH4-SiO2. Moreover, the electrical properties of the SiO2 stacks were shown to be strengthened in comparison with their single-layer counterparts. This is owing to the mutual interactions between hydrogen groups in the SiH4-SiO2 and hydroxyl groups in the TEOS-SiO2. Top-gated indium–tin-oxide-stabilized ZnO TFTs with stacked gate insulators (GIs) were demonstrated after the optimizations of the GI layer thickness and deposition order and were shown to be free of hysteresis with a high ON–OFF ratio of over 1010 and a sharp subthreshold swing of 96.9 mV/decade. The combination of TEOS-SiO2 and SiH4-SiO2 initiates an economical strategy to achieve reliable GIs for high-performance top-gated metal-oxide TFTs.