Higher Reliability Tetraethylorthosilicate SiO2 Gate Insulator in Polysilicon Thin Film Transistors Formed by Two-Step Deposition Method

Abstract

Tetraethylorthosilicate (TEOS)-SiO2 formed by two-step plasma enhanced chemical vapor deposition (PECVD) was investigated as gate insulator for low temperature polycrystalline silicon thin film transistors (TFTs). The TEOS-SiO2 deposited at higher RF power conditions showed better reliability than TEOS-SiO2 deposited at lower RF power. The higher reliability of TEOS-SiO2 at higher RF power conditions was stem from the structural improvement of TEOS-SiO2. But TEOS-SiO2 deposited at higher RF power induced higher plasma damage on the interface so that two-step deposition method was introduced to avoid interface damage that can be measured by TFT characteristics such as s factor and mobility of TFTs. For the two-step deposition of gate insulator, 100 Å-thick TEOS-SiO2 with low RF conditions was deposited first. Then TEOS-SiO2 with high RF conditions was deposited about 900 Å-thick. The gate insulator with two-step deposited TEOS-SiO2 showed similar electrical reliability with gate insulator that was entirely deposited at high RF power conditions. Besides, the two-step deposited gate insulator showed superior interface characteristics than the gate insulator with high RF power conditions. These results indicate that two-step deposition of gate insulator improves gate insulator reliability without deteriorating interface characteristics between active layer and gate insulator.