Future Directions for Through Silicon Vias

Abstract

Die stacking using Through Silicon Vias (TSVs) is a promising path for short, dense, and low capacitance interconnects. Logic to memory and logic to logic stacking are specific examples of applications which directly benefit from TSV technology. Low capacitance TSVs offer power efficient path to reach > 1TB/s bandwidths. In the case of logic-to-logic stacking power can be reduced by up to 50% for a deeply pipelined machine (1). Despite clear technical advantages prolific adoption of TSV technologies has been limited in part by implementation costs. Materials and equipment improvements are improving the probability of finding TSV based stacking applications which justify the cost. Continued scaling will further reduce costs and create ongoing material and equipment opportunities and opportunities for new TSV applications. After reviewing specific logic to memory and logic to logic applications, future scaling directions will be discussed.