Abstract
3D WLCSP using via last TSV (through silicon via) technology is an ideal packaging technology to meet small-form-factor, lightweight, low-profile, high I/O density, high-speed and most important, lower cost. For thin 3D WLCSP with TSVs, a number of critical processes need to be developed. Because of the applying of the temporary adhesive for device and carrier wafer bonding, process integration steps where high temperature tolerance are critical include silicon etch, PECVD, and PVD. In addition, some processes, like oxide etch, via cleaning and wafer de-bonding are quite challenging. In present paper, 8 inch, thin WLCSP using via last TSV scheme has been successfully demonstrated. Two temporary materials, named HT1010 and 305 from Brewer Science were used for thin wafer handling process integration. In the package, the diameter of the vertical TSV is 60μm and the final Si thickness is 120μm. Cu/Ni/Au RDL with ∼5μm thickness are fabricated on backside of the chips.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
