Full-scale integration of superconductor electronics for petaflops computing

Abstract

Ultralow-power and ultrahigh-speed single-flux-quantum electronics is an enabling technology solution for near-term petaflops computing. The proposed hybrid technology multithreaded (HTMT) petaflops-scale computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Pbits s-1. In this frequency regime, on-chip interconnect mimics the system interconnect problem. On-chip latency can be minimized with increased gate density by using more levels of metal and smaller line pitch. This may be even more important than increasing the maximum clock rate by using smaller junctions and higher critical current density. Superconductor ICs at an integration level of 100k gates cm-2 are proposed for the processors, first-level cache and interprocessor network. Petaflops capacity will require a compact, optimized system-level packaging strategy to achieve the necessary computational density and interconnect bandwidth. Modular packaging and automated circuit testing are required to minimize manufacturing costs. We focus on the critical technology challenges that exist for the IC foundry, packaging and the I/O data link and present technology roadmaps to achieve the HTMT requirements.