Superconductor Electronics for Petaflops Computing and Beyond

Abstract

A Petaflops computer represents a thousand-fold improvement over today’s largest massively-parallel-processor machines, which are susceptible to fundamental time-of-flight and power dissipation limits. Ultra-low power and ultra-high speed single-flux-quantum electronics is an enabling technology solution for near-term petaflops computing. The proposed Hybrid Technology Multi-Threaded (HTMT) petaflops-scale computer architecture includes thousands of superconductor computational modules operating at 100 GHz with an I/O throughput of 40 Petabit/s. This presents challenges in integration level of superconductor ICs, RAM size and access time, chip- to-chip and out-of-dewar I/O, modular packaging, power supply, and power dissipation. The HTMT system concept and the requirements it places on the cryogenic processing unit are described. The feasibility and path to high gate count, high clock rate SCE chips at an integration level of >100 kgates/cm2 for the processors, cryogenic RAM, and inter-processor network are addressed. Compact, optimized system-level packaging is necessary to achieve the computational density and interconnect bandwidth. Modular packaging and automated circuit testing are required manufacturing costs. Critical technology challenges that exist for packaging, testing, and the I/O datalink are discussed.