FSM Decomposition and Functional Verification of FSM Networks

Zafar Hasan,Maciej J Ciesielski

doi:10.1155/1995/62636

Abstract

Here we present a new method for the decomposition of a Finite State Machine (FSM) into a network of interacting FSMs and a framework for the functional verification of the FSM network at different levels of abstraction. The problem of decomposition is solved by output partitioning and state space decomposition using a multiway graph partitioning technique. The number of submachines is determined dynamically during the partitioning process. The verification algorithm can be used to verify (a) the result of FSM decomposition on a behavioral level, (b) the encoded FSM network, and (c) the FSM network after logic optimization. Our verification technique is based on an efficient enumeration-simulation method which involves traversal of the state transition graph of the prototype machine and simulation of the decomposed machine network. Both the decomposition and verification/simulation algorithms have been implemented as part of an interactive FSM synthesis system and tested on a set of benchmark examples.

Highlights

Equential circuits play a major role in the control part of digital systems and efficient computer-aided design tools are essential for their design
Given that the logic implementation of an Finite State Machine (FSM) is derived from its state transition graph (STG) specification, followed by state assignment and intensive logic optimization, this cost function does not reflect the true complexity of the eventual logic-level implementation and is often far from accurate
The decomposition method described has been implemented as a C program which is part of a larger interactive FSM synthesis system [26]

Summary

Introduction

Equential circuits play a major role in the control part of digital systems and efficient computer-aided design tools are essential for their design. Implementing a finite state machine as a network of interacting submachines can be advantageous as it improves the performance of FSM controllers; this, in turn, may significantly affect the system clock. The FPGA and PLD logic is realized by means of interacting logic blocks, with restrictions on the number of I/O lines per block and sometimes on the number of product terms per block 15] In many cases it is desirable, for reasons. Our decomposition approach aims at optimizing the performance of the resulting implementation This is in contrast with other methods, such as [3], where the emphasis is on reduction of circuit area only. Previous approaches to FSM decomposition have used the number of states and the number of edges in the resulting submachines as their cost function Our technique uses a more accurate estimate based on symbolic minimization of the FSM

Methods

Results

Conclusion