Abstract
A standard cell library for implementing Rensselaer's fast reduced instruction set computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps. >
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