FPGA-based Design System for a Two-Segment Fibonacci LFSR Random Number Generator

Abstract

For a long time, random numbers have been used in many fields of application. Much work has been conducted to generate truly random numbers and is still in progress. A popular method for generating random numbers is a linear-feedback shift register (LFSR). Even though a lot of work has been done using this method to search for truly random numbers, it is an area that continues to attract interest. Therefore, this paper proposes a circuit for generating random numbers. The proposed circuit is designed to produce different sequences of numbers. Two segments of Fibonacci LFSR are used to form a generator that can produce more varied random numbers. The proposed design consists of blocks: segment 1, segment 2, and a clock controller. The system produces random numbers based on an external clock. The clock signal for the first segment is that of the external clock, whereas that for the second segment is modified by the clock controller. The second stage (segment 2) is executed only after every 2<em><sup>n</sup></em><sup>1</sup>−1 clock cycles. The proposed design can generate different sequences of random numbers compare to those of the conventional methods. The period of the proposed system is less than that of the original Fibonacci LFSR. However, the period is almost equal to the original one when the system is realized in 32-bit or 64-bit form. Finally, the proposed design is implemented on a field-programmable gate array (FPGA). It occupies more area and runs at a lower frequency compared with the original Fibonacci LFSR. However, the proposed design is more efficient than the segmented leap-ahead method concerning space occupancy.