FPGA implementation of the binary pulse compression sequences with good merit factor

Abstract

This paper describes the FPGA implementation for the Binary Pulse Compression Sequences based on Merit Factor using an efficient VLSI architecture. The Proposed architecture is a novel and efficient architecture as it identifies the good binary pulse compression sequences based on Merit factor. So far, no known hardware architecture was reported in the literature for the identification of good Pulse Compression sequence. Binary codes have been widely used in radar and communication areas, but the synthesis of Binary codes with good Merit Factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. However, there is no guarantee to get global optimum point. In this paper, a novel and efficient VLSI architecture is proposed to design Binary Pulse compression sequences with good Merit Factor. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability. The implemented architecture overcomes the drawbacks of non guaranteed convergence of the earlier optimization algorithms.