DESIGN AND IMPLEMENTATION OF VLSI ARCHITECTURE FOR GENERATION OF TERNARY PULSE COMPRESSION SEQUENCE BASED ON CHARACTERISTIC PARAMETERS

Abstract

This paper describes the VLSI implementation for identification of characteristic parameters of the given ternary pulse compression sequence and also generates the ternary pulse compression sequence for transmission purpose if the characteristic parameter satisfies certain required value. In this paper an efficient VLSI architecture is proposed to calculate the characteristic parameters of the given ternary pulse compression sequence simultaneously or separately. The hardware architectures reported in the literature till now have the capability of identification of only one characteristic parameter of the ternary pulse compression sequence. In this paper an effort is made for proposing an efficient VLSI architecture for identification of the characteristic parameters i.e. merit factor and discrimination of the ternary pulse compression sequence either simultaneously or separately. If the identified characteristic parameter satisfies certain required value then the proposed architecture in this paper automatically generates the ternary pulse compression sequence for transmission purpose. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability.