Abstract

Radar signal processing applications require a set of sequences with individually peaky auto correlation and pair wise cross correlation. Obtaining such sequences is a combinational problem. If the auto correlation and cross correlation are taken in the aperiodic sense then there are hardly any theoretical aids available. The main criterion for good pulse compression sequence is the Merit factor and discrimination. Thus the problem of signal design referred to above are challenging problem for which many global optimization algorithms like genetic algorithm, simulated annealing, tunneling algorithm were reported in the literature. All these optimization algorithms have serious drawbacks of non guaranteed convergence, slow convergence rate and require large number of evaluations of the objective function. To overcome these drawbacks, recently we proposed an efficient VLSI architecture for identification of the six-phase pulse compression sequences. Integrating this architecture with the currently proposing architecture provides an efficient real time hardware solution for identification and generation of the Six phase pulse compression sequences. This paper describes the generation of the Sixphase Pulse compression sequences using field programmable gate array (FPGA). The proposed VLSI architecture is implemented on the FPGA as it provides the flexibility of reconfigurability and reprogrammability.

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