FPGA implementation of rule optimization for stand-alone tunable fuzzy logic controller using GA

Bhaskara Rao Jammu,Pushpak Pati,K K Mahapatra,S K Patra

doi:10.1007/s40747-016-0017-5

Abstract

In this paper, self-tuned, rule-optimized multi-input and multi-output (MIMO) fuzzy logic controller (FLC) is implemented on field programmable gate arrays (FPGA). The design of membership functions, rule base are made with aid of genetic algorithm (GA). Flexibility in FPGA design is implemented through tuning of FLC parameters. The system is modularized as rule base development, rule base transfer and computations on FPGA. Based on the system, an experimental dataset is obtained, which is utilized in a capable computing platform so as to develop a fine-tuned fuzzy rule base. The synthesized rule base is transferred to FPGA along with user provided inputs through a GUI. The GUI also displays the output result sent by FPGA. The communication between the GUI and the FPGA is done via universal asynchronous receiver and transmitter. Rule-optimized FLC is implemented on Xilinx Virtex-5 LX110T board. This dedicated single chip architecture performs high-speed fuzzy inferences with processing speed up to 760 KFLIPS at a clock frequency of 247 MHz using 8 rules, 2 input variables at 16-bit resolution. Experiments of software implementation and hardware software co-design implementation are presented and compared.

Highlights

Fuzzy logic controllers (FLC) have immensely contributed to the industrial sector [1,2,3,4]
Once the rule base has designed the parameters of the rules, input variables and control information are sent through serial communication protocol like RS-232 of the computer to the UART module of the Xilinx board and saved in the dual-port block RAM on the field programmable gate arrays (FPGA) through its Port A
The optimized fuzzy rule base was sent to the designed FPGA model to predict the data for the same 1000 data points

Summary

Introduction

Fuzzy logic controllers (FLC) have immensely contributed to the industrial sector [1,2,3,4]. Once the rule base has designed the parameters of the rules, input variables and control information are sent through serial communication protocol like RS-232 of the computer to the UART module of the Xilinx board and saved in the dual-port block RAM on the FPGA through its Port A. This completes the updating of the rule base at the hardware level. The software part is done in the personnel computer (PC) for the designing and tuning of the rule base and the hardware section includes real-time implementation of the FLC on the XUPV5LX110T board.

Implication model

Findings

Conclusion