FPGA Implementation of a Face Detector using Neural Networks

Abstract

The study implemented an FPGA-based face detector using neural networks. We used a floating point arithmetic unit (FPU) to represent the number system. The FPU provides dynamic range and reduces the bits of arithmetic unit more than fixed point method. These features led to reduction in the memory so that it is efficient for neural networks system with large size data bits. In this system, an FPGA-based face detector using neural networks takes 1.7 ms to process one frame to be 38 times faster than 50 ms of PC (Pentium4, 1.4 GHz). This speed gives a chance to have better picture than PC process and could be named hardware accelerator. The implemented FPGA-based face detector using neural networks also required 33% of total area in FPGA (Xilinx XC3S1500) which could be applied to a stand-alone system. In order to determine the bits of FPU, we also examined how representation errors affect a detection rate. The arithmetic unit occupies 84%, occupying most of the available area. Therefore bits reduction is needed not only for memory but also for FPU and system size. Reduction from FPU 32 bits (IEEE 754 single precision) to 24 bits reduced the size of memory and arithmetic units by 25%, having only 0.32% deterioration in the detection rate