Floating Point Arithmetic Unit with Multi-Precision for DSP Applications

Abstract

In digital signal processing, the arithmetic of floats is very significant. The arithmetic float point unit, which is normally selectable for various precision floating point numbers, is able to work at different precision floating point numbers among various types of engineering application. Flexible architecture of floating point arithmetic is provided by the accelerated growth of the FPGA technologies. This paper explains how a common floating point arithmetic method based on FPGA is constructed using Verilog HDL. The arithmetic floating point unit is capable of supplementing and subtracting a few double precision float point numbers or two singles. The floating point arithmetic unit will execute a pair of double-precision floating point numbers or two single-precision floating point numbers. At the conclusion of this article, simulation and hardware test illustrate functionality and measurement correctness.