Abstract
Abstract —Floating point arithmetic is very important in digital signal processing. It’s usually to select different precision floating point numbers among various kinds of engineering application, this makes the floating point arithmetic unit capable of operating on different precision floating point numbers. The rapid development of FPGA technology provides the possibility for the flexible design of floating point arithmetic. This paper describes the process of building a general floating point arithmetic unit using Verilog HDL based on FPGA. The floating point arithmetic unit can perform addition and subtraction operations of a couple of double precision floating point numbers or two couple of single precision floating point numbers. At the end of this paper, the features and calculation correctness are proved through simulation and hardware experiments.
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