FPGA Benchmarking Structures Dedicated to TID Parametric Degradation Evaluation

Abstract

This article presents a cost-effective and efficient methodology to evaluate and compare parametric degradation of FPGA performance induced by total ionizing dose (TID). At the component level, TID causes increased power consumption and an altered propagation delay of the logic elements. These parametric deviations must be evaluated to be properly considered in the design margins. Dedicated benchmarking structures have been developed to evaluate the propagation delay evolution of logical resources and routing elements of the FPGA. An embedded system based on the reprogrammable feature of embedded PLLs has been implemented to continuously measure <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> the propagation delay evolution during radiation experiments with limited instrumentation. Particular attention was paid to the decoupling of thermal effects and direct TID effects. The effectiveness and benefits of this methodology are demonstrated through X-ray radiation tests. Test results on three FPGA families: Xilinx Spartan7, Artix7, and Intel Cyclone10LP are presented, compared, and discussed.