Abstract
With the development of integrated circuit technology, design for test (DFT) is on the agenda. In this paper, we propose a new method that the non-test part of a SIP chip can be easily tested with the boundary-scan test utilizing the boundary scan chain of the FPGA. The problem of no boundary scan test structure in one (or more) chip in a system-in-package (SIP) can be solved by connecting the interconnection (s) to be tested to the FPGA to form an enlarged boundary scan daisy chain.
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