Abstract
A four-quadrant current multiplier circuit is presented. It is based on the current-mode approach and the square-law characteristics of a MOS transistor in saturation. The analog multiplier is realized by using two squarer circuits biased by a common biasing network. Simulation was carried out using Pspice 7.1, with SCNA parameters obtained through MOSIS. Simulation results show that, for a power supply of /spl plusmn/3 V, the multiplier has a -3 dB bandwidth of 10.7 MHz. The total harmonic distortion is less than 0.14% with input ranges up to /spl plusmn/97.5 /spl mu/A. The multiplier circuit is used as a phase-detector. The transfer characteristics of the detector is obtained and the piecewise linearization is performed.
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