Abstract
A /spl plusmn/1 V four-quadrant analog BiCMOS multiplier is presented. The design is based on the current-mode approach and uses the square-law characteristics of a MOS transistor in saturation. The new multiplier utilizes I-V converters, current-mirrors, and only two power supplies to achieve high linearity and superior performance.
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Published version (
Free)
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
