Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

Abstract

Two methods are proposed to fabricate stacked ruthenium (Ru) nanocrystals (NCs): rapid thermal annealing (RTA) for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2–4 nm and 3 × 1012 cm−2 for the former method, compared to 3–7 nm and 2 ×1012 cm−2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor (MOS) capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.