Formation of lateral SiGe tunneling field-effect transistors on the SiGe/oxide/Si-substrate

Abstract

A lateral SiGe tunneling field-effect transistor (TFET) with excellent electrical characteristics has been implemented on a SiGe/oxide/Si-substrate (SGOI) wafer. For this SiGe TFET device biased at a drain voltage of 1 V and a gate voltage of 1 V, the resultant on-state current is about 120 µA µm−1 and the off-state leakage is only about 2 pA µm−1, for a gate length of 0.2 µm. However, the SiGe MOSFET device would correspondingly yield a high leakage current, due to serious source/drain punch-through. Hence, the TFET structure may easily implement a transistor with excellent characteristics, without the need of intensive process and device integration in the MOSFET structure. With further scaling of the gate length down to 0.1 µm, prior to the source/drain implantation, an additional oxide spacer should be employed to reduce the strong lateral electric field induced by a short channel, thus suppressing the considerably enhanced leakage current. However, for the 0.1 µm and the 0.2 µm device schemes, the resultant electrical characteristics and the layout area are comparable. As a result, for this SiGe TFET device biased at a low power supply voltage of 1 V, the gate length of about 0.1–0.2 µm may just provide an optimal design of such a device, which causes an on/off ratio of about eight orders.