Abstract
Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design. To achieve this, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in the validation process. The Event-B method is a promising formal approach that can be used to develop, model and prove accurately SoC and MPSoC architectures. This paper proposes a formal verification approach for NoC architecture including the dependability constraints relating to the choice of the path routing of data packets and the strategy imposed for diversion when faulty routers are detected. The formalization process is incremental and validated by correct-by-construction development of the NoC architecture. Using the concepts of graph colouring and B-event formalism, the results obtained have demonstrated its efficiency for determining the bugs, and a solution to ensure a fast and reliable operation of the network when compared to existing similar methods.
Highlights
Introduction and Related WorkThe growing chip complexity and the need to integrate more and more components on the chip imposes the trend for embedded systems moving towards Multiprocessor System-on-Chip (MPSoC)
The main originality of the proposed routing algorithm based on the bypass rules is that the routing is performed in the activated area depending on the number of faulty nodes or regions where, in the case of a rectangular region, the activated nodes form a ring around the region and the routing in activated area is reduced to route along the formed ring
We have proposed a formal method using Event-B to specify, verify and prove the behaviour of fault tolerant routing scheme suitable for design reliable or adaptive NoC architectures
Summary
The growing chip complexity and the need to integrate more and more components on the chip (e.g., processors, DSP cores or memories) imposes the trend for embedded systems moving towards Multiprocessor System-on-Chip (MPSoC). In the new SoC paradigm, the network centric approaches, called Networks-on-chip (NoCs), are progressively becoming the main on-chip communication mediums and are the major issue in MPSoC. Integrating a NoC in the SoC provides an effective way to interconnect several Processor Elements (PEs) or Intellectual. Properties (IPs) (processors, memory controllers, etc.) [1], with high levels of modularity, flexibility, and throughput. A NoC consists of routers and interconnections allowing communications between PEs and/or IPs. Communication on NoC relies on data packet exchanges. Correctness of such communicating structure should be ensured.
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