Flip-Flop SR Latch and Half-Adder Logic Circuit Configuration Using SOT-MT J

Abstract

We present SPICE simulation results of a novel Flip-Flop SR Latch and Half-Adder logic that operates at faster switching times and lower switching energies. Spin orbit torque (SOT)-magnetic tunnel junctions (MTJs) are suitable for logic operations due to its ability to isolate its read and write paths as well as other properties such as non-volatility and scalability. In this work we propose and demonstrate SOT-MTJ based spin logic architectures using SPICE. A Half-Adder and SR-Latch structure constructed using SOT-MTJs in a circuit configuration are tested. Our circuits have been found to require lesser devices (transistors), faster switching times and lower switching energies as compared to its conventional semiconductor counterparts. The results are summarized in Tables 1 & 2. Table 1. Comparisons between 180nm CMOS, carbon nanotube field effect transistor (cnfet) and SPICE SOT-mtj model for a flip flop SR-latch logic. Device/Model Switching Time (ps) Energy Delay (10−24 J-s) 180nm CMOS 160 6.77 CNFET [1] 14.4 $7 \text{x} 10^{-4}$ SPICE SOT-MTJ 1.02 $4.1 \text{x} 10^{-6}$ Table 2. Comparisons between 180nm CMOS gate diffusion input (gdi), 180nm CMOS MUH and SPICE SOT-mtj model for a half-adder logic. Device/Model Switching Time (ps) Energy Delay (10−24 J-s) 180nm CMOS (GDI) [2] 48.25 $2.56 \text{x} 10^{-2}$ 180nm CMOS (MUH) [2] 34.9 $1.27 \text{x} 10^{-2}$ SPICE SOT-MTJ 1.02 $8.69 \text{x} 10^{-6}$