Flip chip CSP assembly with Cu pillar bump and molded underfill

Abstract

Flip chip package has matured significantly over the past several years, shifting from conventional eutectic Sn-Pb solder bump to Pb-free interconnection. It has become the preferred package solution for high performance IC and microprocessor device. From the last decade, there has been a significant focus on the development of Cu pillar bump interconnection in flip chip package which could meet current and future requirement of tighter bump pitch and smaller bump driven by the scaling of silicon feature size. Moreover, the manufacturing cycle time and assembly cost could be decreased by using molded underfill (MUF) encapsulation instead of the combination of capillary underfill (CUF) and epoxy molding compound (EMC). In this paper, we summarize some of the development work of high density Cu pillar bump flip chip assembly with MUF. The die size of the test vehicle is approximately 6x6mm incorporating Cu pillar bump with Sn-Ag cap whose miniature pitch is 90um. The strip configuration is 240x76mm with 2 layers lamination structure. The final FCCSP package body size is 12x12mm. This paper details mold flow numerical simulation and MUF process development. The warpage behavior of FCCSP package impacted by mold flow is investigated. Shadow moire system is employed to characterize the warpage of the signal unit. Reliability tests are measured according to JEDEC standards. Test vehicle has passed internal qualification including MSL3, uHAST 96hrs and TCB 1000 cycles.