Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks

Rafał Długosz,K Iniewski

doi:10.1155/2007/45269

Abstract

A novel 8-bit current mode interleaved successive approximation (SAR) analog-digital converter (ADC) has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tuned to work with different sampling rates, number of bits of resolution, and power consumption levels. Due to its very low-power consumption and flexibility, the converter is particularly suitable for application in wireless sensor networks. Compared to other solutions presented in the literature, the proposed converter achieves very high figure of merit (FOM) value due to numerous low-power circuit innovations utilized in its design. The circuit has been implemented in CMOS 0.18 μm technology. Minimum energy consumption has been found to be in a 25–250 kS/s range (for clock sampling frequency in a 200 kHz--2 MHz range) for a single SAR section with the corresponding power dissipation varying from 220 nW to 560 nW for 0.55 V power supply.

Highlights

Advantages of wireless sensor networks (WSNs) lie in the development of a low-cost, scalable, and flexible network architectures
A typical wireless sensor node consists of a RF front end, an analog to digital converter (ADC), an optional microprocessor to process the collected data, and a power supply block [1]
The goal of this paper is to propose a novel ADC architecture that is suitable for WSN applications

Summary

INTRODUCTION

Advantages of wireless sensor networks (WSNs) lie in the development of a low-cost, scalable, and flexible network architectures. One of the drawbacks of this ADC is a low-voltage swing (0.5 V for VDD = 3 V) and a slightly more complicated architecture of the clock generator that controls the S&H elements Another voltage-mode ADC is presented in [27] implemented in CMOS 2 μm technology and consumes 200 μW from a 5 V voltage supply, enabling a sampling frequency of 50 kHz. The circuit operates with three reference voltages in each conversion stage. An ultra-low-power voltage-mode SAR ADC is presented in [28] This circuit was designed in CMOS 0.25 μm technology and operates with a sampling frequency of 100 kS/s, dissipating only 3.1 μW from 1 V voltage supply. When all eight sections are nonactive (standby mode), which is a desired functionality when the WSN node is in a sleep mode, the entire ADC consumes 130 nW

SAR ADC ARCHITECTURE

PROPOSED INTERLEAVED SAR ADC

CMOS IMPLEMENTATION

Findings

CONCLUSIONS