Abstract
A flash fast-locking digital phase-locked loop (DPLL) is presented using transistor level 50 nm CMOS technology and 1V power supply in LT SPICE. The DPLL operation includes two stages: (1) a coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage consists of frequency comparator array, a priority encoder, a digital-to-analog converter (DAC), and control logic (CL). Design considerations and implementations are presented in this paper. The fast-locking flash DPLL reduces the lock time by a factor of about 2.19 when compared with the conventional DPLL counterpart, in the frequency range 80 MHz–1.1 GHz.
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