A Novel Flash Fast-Locking Digital PLL: Verilog-AMS Modeling and Simulations

Abstract

A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled using Verilog-AMS. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm leading to a thermometer code as done in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage includes an array of frequency comparators, a priority encoder, a digital-to-analog converter (DAC), and control logic including a monostable multivibrator. Verilog-AMS (Smash) is used to design and simulate both the fast-locking DPLL and its classical counterpart. Simulations revealed a lock time improvement (reduction) by a factor of 1.50-3.00 depending on the size of the input frequency hop in favor of the fast-locking DPLL.