A Novel Flash Fast-Locking Digital PLL: VHDL-AMS and Matlab/Simulink Modeling and Simulations

Abstract

A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage includes an array of frequency comparators, a priority encoder, a digital-to-analog converter (DAC), and control logic. Design considerations and implementations are presented in this paper. VHDL-AMS (Simplorer) and Matlab/Simulink are used to design and perform simulations. The fast-locking DPLL reduces the lock time by a factor of about 1.80 compared to its conventional DPLL counterpart.