Abstract
3-D stacking with vertical interconnection of thinned microelectronic silicon chips is a novel approach to achieve the enhanced performance, higher density, and smaller size of integrated circuits with a better multifunctionality than the traditional 2-D chip packaging. To achieve this, high alignment accuracy is required between the top chip and the bottom substrate along with good bonding between the two intermediate surfaces. In this paper, a novel approach to stacking is proposed: rapid heating self-aligned assembly. Using this approach, fast and good intermediate dielectric bonding is realized along with high alignment accuracy between the top chip and the bottom substrate compared with the similar process at room temperature. This approach can be used for die-to-die bonding and die-to-wafer bonding for 3-D and MEMS applications.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have