Abstract

This paper presents an efficient platform for fault robustness estimation of digital circuits. The proposed platform, named FIFA, was designed as a hardware IP to accelerate the Fault Injection and Fault masking Analysis approach. It supports several fault models as well as single and multiple faults. Synthesis results have shown that the proposed platform can exceed those existent in the literature in terms of area efficiency and performance. In addition, the FIFA platform allows the designer to control complexity and completeness of the analysis process.

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