Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

Abstract

A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.