Abstract
Since the early 1960s, semiconductor chips have matured from single transistor devices to 1 million transistors per chip. This increase in integration has been achieved by reducing transistor dimensions, and by increasing chip sizes. However, physical limits are being reached as submicrometre dimensions are approached. Therefore, there is need for larger chip, and wafer, sizes. Manufacturers use defect tolerance to maintain the increase in chip complexity; acceptable yields are achieved with larger chip sizes. In the paper, various aspects of defect-tolerant design are investigated. It is suggested that yield improvement is only one of the many possible gains offered by defect tolerence. The advantages and disadvantages of the many approaches to defect tolerance are discussed. Wafer-scale integration appears to be the target size for defect tolerant IC chips, but as wafer size continues to increase, the constraints due to wafer-scale implementation of an architecture must be weighed up against the advantages that such devices offer. The paper also examines a particular subsystem implemented in VLSI, ULSI and WSI, and considers the relative merits of each implementation.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEE Proceedings E Computers and Digital Techniques
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
