Challenges facing practical DFT for MEMS

Abstract

Defect and fault tolerance techniques have played a substantial role in the evolution of silicon digital integrated circuits (ICs). The complex and several mechanisms causing defects in the as-manufactured IC could be represented by simple functional defects (stuck-at faults, etc.) and. given these simple functional defects, a variety of testing techniques (including built-in self-test) could be deployed. Defect tolerance by reconstructing an IC emerged rather early in RAMs and in various array-based architectures. Field-useable testing techniques capable of isolating the site of a defect causing a functional failure farther extended capabilities to allow field-correction or self-correction when failures occurred. Analog ICs present a more sophisticated challenge, though several capabilities for defect tolerance (e.g., laser adjustment of resistances or capacitances) and for fault tolerance (including modular redundancy) emerged. The microelectromechanical systems (MEMS) technology (also called microsystems technology-MST) has matured to the point where more extensive applications can be commercially realized. moving beyond the relatively limited number of significant commercial applications now seen. Addition of defect and fault tolerance to the MEMS technology in a manner which abstracts details to achieve simple models will, however, be difficult.