Fault simulation techniques for fabrication verification: a perspective

Abstract

It is noted that the benefit of grading test vectors by fault simulation results in a savings of both time and money during the test stage for the detection of manufacturing defects. Accuracy, cost, and processing time are important features to be considered when evaluating fault simulation methods. It is suggested that the answer to which fault simulation solution is right needs to be evaluated on a case-by-case basis. It is shown that, although deterministic fault simulators are slow, they are and will be popular in the future because of their accuracy and hostability on general-purpose computers such as CAE (computer-aided engineering) workstations. Parallel processing methods lend themselves very nicely to fault simulation. With the widespread use of CAE workstations that are often connected together via a communication network, the hardware is already configured in a manner that is ready for parallel processing applications. An adequate trade-off between speed and accuracy can be obtained through the use of both a deterministic fault simulator and a statistical-based method. >